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Foxton was an Intel code-name for a power-management technology that was originally planned for inclusion in the first dual-core Itanium 2 processor (code-named Montecito).^[1] By providing very granular control of voltages and clock frequencies within the processor, it was intended to enable software performance to be optimized for specific workloads, while ensuring that power consumption remained below a particular value.^[1] Due to unspecified issues, Foxton was not included in the initial release of Montecito.^[2] According to sources inside Intel at the time, it was under consideration for future Itanium 2 processor versions. It does not appear to have been used in any Itanium processor before the entire product line was dropped by Intel.

Foxton included a highly advanced clock generation and distribution network. With this technology, the processor continuously measured total power draw, processor loads, voltage, and clock distribution quality across the entire device, and was able to produce extremely fine clock-to-voltage granularity under dynamic conditions. As a result, Foxton enabled a processor to override factory adjusted settings, which are set at relatively high voltage levels at any given frequency to ensure stability against random voltage variances. By dynamically controlling voltage and frequencies across the entire device, Foxton was able to optimize performance for specific workloads, while ensuring that power consumption remained below specified thresholds.

Foxton improved power efficiency at any given clock rate, but that was not the primary reason it was developed. Itanium 2 processors implemented a wide microarchitecture, which had enormous potential computing capacity (theoretically capable of sustaining a throughput of six instructions per cycle). However, most software applications could not utilize all the available execution resources, lacking adequate instruction-level parallelism. Idle resources mean lower transistor switching activity, thus lower overall power consumption. Because Itanium 2 had a wide architecture, the decrease in power consumption for average code execution could be substantial. Since modern MPUs clock rates are constrained by power, not filling out the power envelope translates to lost performance. Foxton took advantage of this decrease by increasing clock frequencies to accelerate performance, while keeping total power consumption below specified thresholds. The result was intended to be a processor architecture that could dynamically optimize performance versus power consumption across a broad range of workloads.

A Foxton-enabled chip had a variable voltage and frequency adjusted to a nominal power envelope that could be specified from software. Clock and voltage were adjusted to keep the chip's consumption within the envelope. Depending on the actual usage pattern the chip was able to scale up or down, feeding the core with proper voltage. Under so called "low activity" workloads, which generate less heat while being executed, the processor speeds up until it reaches the nominal power setting. Inversely, "high activity" loads may cause the chip to reduce core voltage and clock rate to stay below the nominal power setting. Low-activity workloads typically include integer-intensive computations, such as commercial and database applications. Foxton was expected to increase performance for these applications by about 10% compared with the same processor running with a "fixed clock."^[1] High activity workloads include floating point-intensive computations, such as scientific and R&D simulations. Nominal clock speeds for Itanium processors with Foxton would have been based on power consumption for these intensive computations.

Intel planned for Foxton to not only appear in the Itanium family, but later in Xeons as well.^[1]

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