The Intel Ultra Path Interconnect (UPI)[1][2] is a scalable processor interconnect developed by Intel which replaced the Intel QuickPath Interconnect (QPI) in Xeon Skylake-SP platforms starting in 2017.
Interconnect
[edit]UPI is a low-latency coherent interconnect for scalable multiprocessor systems with a shared address space. It uses a directory-based home snoop coherency protocol. Data on the UPI bus can be transferred in both directions simultaneously. Transfer speed of UPI 2.0 link reaches 24 GT/s (48 GB/s per direction per link). Supporting processors typically have two or three UPI links.
Comparing to QPI, it improves power efficiency with a new low-power state, improves transfer efficiency with a new packetization format, and improves scalability with protocol layer that does not require preallocation of resources.
UPI only supports directory-based coherency, unlike previous QPI processors which supported multiple snoop modes (no snoop, early snoop, home snoop, and directory).
A combined caching and home agent (CHA) handles resolution of coherency across multiple processors, as well as snoop requests from processor cores and local and remote agents. Separate physical CHAs are placed within each processor core and last level cache (LLC) bank to improve scalability according to the number of cores, memory controllers, or the sub-NUMA clustering mode. The address space is interleaved across different CHAs, which act like a single logical agent.
See also
[edit]References
[edit]- ^ David Mulnix (September 14, 2017). "Intel® Xeon® Processor Scalable Family Technical Overview". Intel Corporation. Retrieved September 17, 2017.
- ^ "The Mesh Topology & UPI - Intel Xeon Platinum 8176 Scalable Processor Review". 11 July 2017.
External links
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Interfaces are listed by their speed in the (roughly) ascending order, so the interface at the end of each section should be the fastest.  Category | |
