Technopedia Center
PMB University Brochure
Faculty of Engineering and Computer Science
S1 Informatics S1 Information Systems S1 Information Technology S1 Computer Engineering S1 Electrical Engineering S1 Civil Engineering

faculty of Economics and Business
S1 Management S1 Accountancy

Faculty of Letters and Educational Sciences
S1 English literature S1 English language education S1 Mathematics education S1 Sports Education
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Flag Counter
  2. World Encyclopedia
  3. Socket C32 - Wikipedia
Socket C32 - Wikipedia
From Wikipedia, the free encyclopedia

Socket C32
TypeLGA-ZIF
Chip form factorsFlip-chip
Contacts1207
FSB protocolTwo HyperTransport 3.1 links operating 6.40 GT/s or two HT 1.1 links operating at 800 MHz
ProcessorsAMD Opteron 4000 series
PredecessorSocket F
VariantSocket G34
SuccessorSocket SP3
Memory supportDDR3
This article is part of the CPU socket series

Socket C32 is a zero insertion force land grid array CPU socket designed by AMD for their single-CPU and dual-CPU Opteron 4000 series server CPUs. It is the successor to Socket AM3 for single-CPU servers and the successor for Socket F for lower-end dual-CPU servers (High-end dual-CPU servers will use Socket G34). Socket C32 supports two DDR3 SDRAM channels. It is based on the Socket F and uses a similar 1207-pin LGA socket but is not physically or electrically compatible with Socket F due to the use of DDR3 SDRAM instead of the DDR2 SDRAM that Socket F platforms use.

Socket C32 was launched on June 23, 2010 as part of the San Marino platform with the four and six-core Opteron 4100 "Lisbon" processors.

Socket C32 also supports the Bulldozer-based six- and eight-core "Valencia" Opterons introduced in November 2011.

Both Socket C32 and its contemporary Socket G34 were succeeded in 2017 by Socket SP3 for both single- and dual-CPU servers, supporting Zen-based Epyc CPUs, the successors to all families of Opteron CPUs.

Chipsets

Like Socket G34, it also uses the AMD SR5690, SR5670, and SR5650 chipsets. Socket C32 is also being used in the ultra-low-power Adelaide platform with the SR5650 chipset and HT1 interconnects instead of HT3.1.

See also

References

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