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Motorola 88110 - Wikipedia

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The MC88110 was a microprocessor developed by Motorola that implemented the 88000 instruction set architecture (ISA). The MC88110 was a second-generation implementation of the 88000 ISA, succeeding the MC88100. It was designed for use in personal computers and workstations.

History

The first technical description of the MC88110 was given in November 1991 at the Microprocessor Forum held in San Francisco. The microprocessor was introduced in 1992, operating at 50 MHz. Users were Data General in their AViiON servers, Harris in real-time UNIX systems and Motorola in their single-board computers. NeXT was to introduce a workstation using the MC88110, the NeXT RISC Workstation, but they left the hardware business and cancelled the product before development had completed.

Description

It implemented extensions to the original ISA, such a separate floating-point register file, extended-precision (80-bit) floating-point data types and new integer and graphics instructions. It also implemented microarchitectural features previously non-existent in 88000 microprocessors, such as two-way superscalar execution, out-of-order completion and speculative execution. Despite these new features, which corrected some architectural deficiencies in the MC88100, the MC88110 was ultimately unsuccessful and was used in few systems. The MC88110 was succeeded by PowerPC microprocessors Motorola developed jointly with IBM as part of the AIM alliance, but remained available until the mid-1990s.

Externally the 88110 has a von Neumann architecture (single memory for code and data) with a modified Harvard architecture internally (separate instruction and data caches).^[1]^[a]

The MC88110 supported an optional external 256 KB to 2 MB secondary cache. The secondary cache controller was not integrated on the MC88110, but was located on a separate device, the MC88410, to reduce cost.

The die contained 1.3 million transistors and measured 15 mm by 15 mm (225 mm²). It was fabricated in a 1 μm complementary metal–oxide–semiconductor (CMOS) process. The process has three levels of aluminium interconnect and an effective channel length (the distance between the source and drain contacts of the MOSFET transistors) of 0.8 μm. The MC88110 was designed to be shrunk to a 0.8 μm process with an effective channel length of 0.65 μm without modification.

Notes

^ This differs from its predecessor, the 88100, which had a Harvard architecture and required the addition of a pair of 88200 chips to instead use a unified memory.^[2]

References

^ MC88110 User's Manual, Figure 1-3.
^ MC88100 User's Manual, Figure 1-2 and §1.2.7.

Diefendorff, Keith; Allen, Michael (April 1992). "Organization of the Motorola 88110 Superscalar RISC Microprocessor". IEEE Micro. 12 (2): 40–63. doi:10.1109/40.127582. S2CID 25668727.
Tabak, Daniel (1995). Advance Microprocessors (2 ed.). McGraw-Hill. pp. 425–435.
Motorola, Inc., ed. (1991). MC88110 Second Generation RISC Microprocessor User's Manual (PDF). Motorola databook series. OCLC 29333909. Retrieved 25 August 2023.
Motorola, Inc., ed. (1990). MC88100 RISC Microprocessor User's Manual (PDF) (2nd ed.). Prentice Hall. ISBN 013567090X. Retrieved 25 August 2023.

Motorola-Freescale-NXP processors and microcontrollers

Processors
Industrial control unit	14500
6800 family	6800 6809 see also: Hitachi 6309 68HC05 68HC08 68HC11 68HC12 68HC16
68000 family	68000 68008 68010 68012 68020 68030 68040 68060 ColdFire DragonBall
Embedded system 68k-variants	68EC000 68EC020 68EC030 68EC040 68LC040 68EC060 68LC060
88000	MC88100 MC88110
Floating-point coprocessors (FPUs)	68881 68882
Memory management units (MMU)	68451 68851
PowerPC family	PPC e200 PPC 6xx/e300 PPC 7xx PPC e500 PPC 74xx/e600 PPC e5500 PowerQUICC QorIQ PPC e6500
ARM	i.MX

Microcontrollers
8-bit	6801/6803 6802 6804 68HC05 68HC08 S08 RS08 68HC11 68HC12 68HC16
16/32-bit	683xx
24-bit	DSP568xx DSPcontroller
32-bit	M·CORE MPC5xx PowerQUICC PowerPC 5000 i.MX

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